Three phase dc motors, particularly brushless, sensorless, three phase dc motors, are popular in drives in information retrieval systems that use rotating recording media, such as discs. Conventional disc drives are used to both record and to retrieve information. As discs become more prevalent as the medium of choice for storing information in both computer and home entertainment equipment, disc drives likewise become more prevalent and important components of such electronic systems.
In addition to the recording media, a disc drive typically includes a read/write assembly and a spindle motor assembly. The read/write assembly is adapted to transfer data between the disc and an external system, or device, such as a microprocessor. The spindle motor assembly carries the information storage discs and is arranged to rotate the discs.
FIG. 1 is a cross-sectional view of a conventional spindle motor assembly 20 used in disc drives. As depicted, the spindle motor assembly 20 includes a non-rotating spindle flange 22 which may be fastened to a disc drive housing, not shown. A rotatable spindle hub 25 is positioned over the spindle flange 22 and is carried by an elongated rotatable spindle shaft 8 that runs co-axially with the spindle hub 25 and the spindle flange 22. An information storage disc 6 can be positioned over spindle hub 25. The spindle shaft 8 is attached to a motor 34.
The motor 34 includes a stator assembly (or stator) 36 and a rotor assembly (or rotor) 38. The stator assembly 36 includes a plurality of lamination stacks 40 each having a corresponding coil wrapped thereabout. There are three such coils, which will be designated herein as coils A, B, and C, though only coils A and B are specifically shown in FIG. 1. Rotor assembly 38 is attached to spindle shaft 8 by a lower hub 44. The rotor assembly 38 includes a plurality of magnets 50 disposed about the interior surface of a flange 48.
During operation, coils A, B, and C are energized with a drive signal which causes electromagnetic fields to develop about the coils. The resulting attraction/repulsion between the electromagnetic fields of the coils A, B, and C and the magnetic fields created by the magnets 50 causes the rotor assembly 38 and the spindle shaft 8 to rotate about an axis 32. While rotating, the rotor assembly 38 causes a back emf signal to be generated in the coils A, B, and C due to the movement of the magnets 50 in relation to the coils A, B, and C.
The stator 36 can be viewed as having the three coils A, B, and C connected in a "Y" configuration, as shown in FIG. 2, although a larger number of stator coils are usually employed with multiple rotor poles. Typically, in such applications, eight pole motors are used having twelve stator windings and four N-S magnetic sets on the rotor, resulting in four electrical cycles per revolution of the rotor. The stator coils, however, can be analyzed in terms of three "Y" connected coils, connected in three sets of four coils, each physically separated by 90.degree..
The coils are energized in sequences to produce a current path through two coils of the "Y", with the third coil left floating, hereinafter floating coil FC. The sequences are arranged so that as the current paths are changed, or commutated, one of the coils of the current path is switched to float, and the previously floating coil is switched into the current path. The sequences are defined such that when the floating coil is switched into the current path, the direction of the current in the coil which was included in the prior current path is not changed. In this manner, six commutation sequences, or phases, are defined for each electrical cycle in a three phase motor, as shown in Table A.
TABLE A ______________________________________ Phase Current flows From: To: Floating Coil ______________________________________ 1 A B C 2 A C B 3 B C A 4 B A C 5 C A B 6 C B A ______________________________________
FIG. 3 shows a typical architecture of the motor 34 and a driver circuit 10 that drives the motor 34. Individual elements shown in FIG. 3 are suitably made in accordance with prior practice, as described in detail in U.S. Pat. Nos. 5,317,243 and 5,294,877 which are fully incorporated into this specification by reference. Specifically, the motor 34 consists of the stator 36 driven by the driver circuit 10. Although the driver circuit 10 can be constructed of discrete components, preferably, the driver circuit 10 is integrated onto a single semiconductor chip adapted for connection to the stator coils 26a, 26b, and 26c of a three phase dc brushless spindle motor. The stator coils 26a, 26b, and 26c are connected to output nodes OUTA, OUTB, OUTC and CT.
A driving voltage is provided to the stator coils 26a, 26b, and 26c by a power stage 11, which is configured to have one high side driver HSA, HSB, and HSC (not shown) and one low side driver LSA, LSB, and LSC (not shown) for each of the stator coils 26a, 26b, and 26c. The power stage 11 is sequenced to provide sequential control output signals to the stator coils 26a, 26b, and 26c by a sequencer circuit 13. A signal interface circuit 12 supplies the output signals from the sequencer circuit 13 to the power stage 11, as well as enabling other functions, such as brake and output enable functions. The sequencer circuit 13 also provides drive signals to other circuits of the driver circuit 10 through sequence decode and output switches 15 to control the various aspects of rotation of the motor 34.
The stator coils 26a, 26b, and 26c are switchably connected to a back-emf sense amplifier 14. The back-emf sense amplifier 14 in turn delivers signals to a zero crossing detector 16, which provides input signals to a digital timing circuit 17. The timing circuit 17 measures the time between events in the back emf signal. The timing circuit 17 has four counters: a period counter 60, a monotonicity counter 62, a delay counter 64, and a mask counter 66. The output of the delay counter 64 of the timing circuit 17 controls the operation of the sequencer circuit 13.
The driver circuit 10 includes system clock circuitry 23, phase lock loop (PLL) frequency/phase detector circuitry 24, and may include various other circuitry, not shown, such as pulse width modulation (PWM) circuitry to support the PWM operation mode of the motor 34, "align and go" start up circuitry to facilitate the start up of the motor from a stopped condition, port control logic and associated shift register circuitry to facilitate control of the driver circuit 10 by an external microprocessor (not shown), and so forth.
One end of each of the stator coils 26a, 26b, and 26c is connected to a common center tap CT 28. The other end of each stator coil is connected to an output node, respectively designated OUTA, OUTB, and OUTC in FIG. 3. In operation, during an energized phase, one output node, for example node OUTA, is driven high by one of the high side drivers HSA. One output node, for example node OUTB, is driven low by one of the lower side drivers LSB. The third output node, for example node C, is left floating. This is commonly referred to as the "AB phase". The coils are then switched in a commutation sequence determined by the sequencer circuit 13 in a manner such that in each commutation phase current always flows in two of the three coils, with the third coil floating, and that after switching current will continue to flow, and in the same direction, in one of the two coils in which current was flowing in the previous phase to generate the six phases shown in Table A.
The switching of the driver transistors of the power stage 11 to effect the switching currents for each phase is accomplished by the sequencer circuit 13. The sequencer circuit 13 provides signals to the upper driver outputs and the lower driver outputs to accomplish the switching sequence outlined above in Table A.
The commutation among the stator coils 26a, 26b, and 26c is performed in response to information indicating the specific position of the rotor 38 of the motor 34 in conjunction with circuit information indicating the desired position of the rotor 38. More specifically, the commutation to apply the next drive sequence of Table A is determined in response to a corresponding coil reaching a particular rotational position and its correlation with sequencer information indicating where the motor 34 should be when a commutation is to occur. The determination of the precise rotational location of the rotor 38 is continuously being determined by monitoring the zero crossing voltage in each non-driven, or floating, stator coil. More particularly, as the stator coils 26a, 26b, and 26c are switched during the commutation sequence of the rotor 38, the voltage of the floating coil is monitored by the zero crossing detector 16.
During the operation of such a polyphase dc motor, maintaining a known position of the rotor 38 is an important concern. This can be implemented in various ways. One widely used way, for example, has been to start the motor in a known position, then derive information related to the instantaneous or current position of the rotor 38. Such instantaneous position information can be derived during the commutation process by identifying the floating coil and monitoring its back emf, that is, the emf induced into the coil as it moves through the magnetic field provided by the stator 36.
When the voltage of the floating coil crosses zero (referred to in the art as "a zero crossing"), the position of the rotor 38 is assumed to be known. Upon the occurrence of this event, the commutation sequence is incremented to the next phase, and the process repeated. The assumption that the zero crossing accurately indicates the rotor position is generally true if the motor 34 is functioning properly.
The sequence decode and output switches 15 includes switches connected to the stator coils 26a, 26b and 26c through the output nodes OUTA, OUTB, and OUTC to apply a selected one of the output nodes OUTA, OUTB, or OUTC (particularly the output node of the floating coil FC) to the non-inverting input of a comparator in the zero crossing detector 16. The particular one of the output nodes OUTA, OUTB or OUTC which is applied to the comparator corresponds to whichever of coils 26a, 26b, and 26c is expected to be floating (not the coil which is actually floating). Although the term "floating" is used herein to indicate the coil which is not in the instantaneous current path, the coil does not actually "float", but is connected to a tristate impedance.
The center tap connection CT 28 of the stator is connected to the inverting input of the comparator, so that when the voltage on the selected floating coil becomes larger than the center tap voltage, the comparator changes states, representing the zero crossing of the voltage on the selected floating coil. When the voltage on the floating coil becomes smaller than the center tap voltage, the comparator again changes states, representing the zero crossing of the voltage on the selected floating coil. (The voltage on the floating coil is the so-called the back emf of the floating coil.)
The timing circuit 17 measures the time between events in the back emf signal on the floating coil through the four counters: the period counter 60, the monotonicity counter 62, the delay counter 64, and the mask counter 66. The period counter 60 is an up counter that measures the time between successive zero crossings. The period counter 60 is used to determine whether the sequencing of drive pulses applied by the power stage 11 require adjustment, and if so, to initiate corrective action.
After the next successive zero crossing is detected, the count value of the period counter 60 is loaded into the monotonicity counter 62, the delay counter 64, and the mask counter 66, and the period counter 60 is reset in order to count the next period. The monotonicity counter 62, sometimes referred to as a deceleration counter, is a down counter that is used for diagnostic purposes, mainly to detect an abrupt deceleration or stoppage of the motor. The monotonicity counter 62 generally operates at a slower clock rate, such as one-half the rate of the period counter 60 (or operates to detect whether the count for the current period is substantially larger than the count of the previous period). If the monotonicity counter 62 reaches a predetermined count, such as zero, before the period counter 60 resets, a warning of a too-rapid deceleration is given.
The delay counter 64 is an up counter that provides a delay mechanism between the zero crossings and the engagement of the next commutation of the motor. This ensures that the commutation occurs when the torque is at or near its maximum. Typically, the delay time set for the delay counter 64 is about thirty electrical degrees, or around half of the period measured by period counter 60.
The mask counter 66 is an up counter that "masks" the zero detection capabilities in order to reduce or prevent the detection of false zero crossings which may occur due to noise generated under certain conditions, such as upon commutation of the drive between coil paris of the motor 34. A fairly clean back emf signal is needed to detect a true zero crossing. The mask counter disables the back emf amplifier 14 from detecting zero crossings when the mask signal output from the mask counter 66 is active. Typically, the mask time set for the mask counter 66 is about the three-fourths of a period measured by the period counter 60 and the mask period begins right after the detection of a zero crossing.
The delay counter 64 and the mask counter 66 assist in minimizing torque ripple and avoiding the detection of inaccurate signals.
Detection of a false zero crossing, missing the detection of a zero crossing, or incurring a delay in detecting a zero crossing can result in the disk drive read/write head being moved in a backward direction at spin-up. It can also produce jitter in the motor and can disrupt the speed control of the motor. All of this can cause damage to both the disc, the head, and/or the drive components.
One way to improve zero crossing detection in a driver circuit 10 is to improve the resolution of the counters associated with zero crossing detection. In current technology, each of the four counters, the period counter 60 shown in FIG. 4, the monotonicity counter 62, the delay counter 64, and the mask counter 66, includes a series of flip-flops.
To improve the resolution of a counter, the frequency of the clock used to drive the counter can be increased. However, this generally requires adding additional circuitry (additional flip-flops) to be able to detect zero crossings when the motor is spinning up. This increases the die area needed for the counter, and for the drive circuit, and therefore increases the cost of the chip. This goes against some of the central goals of the semiconductor industry to reduce cost and increase the speed of the chip. A low frequency clock would allow a reduction in the number of flip-flops but would not provide high enough resolution in the counters to detect zero crossings. In current technology, an intermediate frequency clock and an intermediate length of flip-flops is used.